Microprocessor including an efficient implemention of an accumulate instruction
US5918062A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1998 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Jan 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution unit configured to perform a plurality of arithmetic operations using the same set of operands. These operands include corresponding input vector values in each of a plurality of input registers. The execution unit is coupled to receive these input vector values, as well as an instruction value indicative of one of the plurality of arithmetic operations. In one embodiment, the plurality of arithmetic operations includes a vectored add instruction, a vectored subtract instruction, a vectored reverse subtract instruction, and an accumulate instruction. The vectored instructions perform arithmetic operations concurrently using corresponding values from each of the plurality of input registers. The accumulate instruction, however, is executable to add together all input values within a single input register. The execution unit further includes a multiplexer unit configured to selectively route the input vector values to a plurality of adder units according to the opcode value. In an embodiment in which the execution unit is configured to perform subtraction operations as well as addition, the multiplexer unit is additionally configured to selectively route negated versions…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.