Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US5918133A · kind A · utility
37Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28194
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and device performance can be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.