Programmable formatter circuit for integrated circuit tester
US5919270A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A formatter circuit for channel of a multiple channel integrated circuit tester includes a drive control circuit, a compare circuit, and a random access memory (RAM). The RAM converts each value of input format selection data to corresponding format control data supplied to the drive control and compare circuits. The drive control circuit generates a set of drive control signals which determine the state of a test signal the tester channel supplies to a terminal of a device under test (DUT). The compare circuit determines whether a DUT output signal at the terminal is of an expected logic state. The drive and compare circuits employ multiplexers controlled by the format control data output of the RAM to select from among a variety of alternative data sources referencing desired states of the drive control signals or expected states of the DUT output signals. The formatter architecture permits flexible use of input reference data to provide a wide variety of selectable drive and compare formats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.