Flash memory with novel bitline decoder and sourceline latch
US5920503A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory with a novel bitline and sourceline decoder includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline. A second bank of flash transistors forms a plurality of rows and a plurality of columns, and has wordlines, bitlines and a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline and sourceline decoder is coupled to the bitlines and sourcelines and configured to receive a bitline address signal and to decode the bitline address signal to select predetermined bitlines and sourcelines. The bitline and sourceline decoder includes a latch coupled to the bitlines, the first sourceline and the second sourceline and configured to latch selected bitlines and sourcelines to selectively provide erase voltages on the selected bitlines and sourcelines. As a result of the novel memory architecture, a flexible number of bytes can be selected for erasure. The selected number of bytes can range from one byte to 64K bytes or more. Advantages of the inventi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.