Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
US5920515A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.