Synchronous clock generator including delay-locked loop
US5920518A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Feb 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data and command latching circuit includes a delay-locked loop driven by a continuous reference clock signal that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit also includes a variable delay circuit external to the delay-locked loop that is driven by a discontinuous reference clock signal. Delay of the external delay circuit is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal. The delayed clock signals from the delay-locked loop activate control data latches to latch control data arriving at the latch circuit. The delayed signals from the variable voltage circuit activate data latches to latch data arriving at the latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.