Architecture and method for controlling a cache memory
US5920891A · kind A · utility
13Cited by
21References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 1996 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | May 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory locations. A bus bridge provides an interface between the first bus and the second bus. A cache memory controller for caching data stored in the cacheable memory locations is connected to the system memory. The cache memory controller includes a snoop control circuit directly coupled to the first bus for snooping bus transactions upon the first bus and further coupled to the second bus for snooping bus transactions on said second bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.