Source biasing in non-volatile memory having row-based sectors
US5923585A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Jan 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory includes an array of memory cells that is partitioned into sectors with sources of memory cells in each sector coupled together but electrically isolated from sources of memory cells in other sectors. Each sector includes one or more rows of memory cells, and sources of memory cells in each row are coupled together by a source-line. During programming of a selected memory cell, a bias circuit grounds a source-line in the sector containing the selected memory cell and applies a bias voltage to the source-lines in the other sectors. The bias voltage reduces program disturb of memory cells that are connected to the same bit-line as the selected memory cell. The bias circuit is coupled to address decode circuitry that indicates which source-line should be grounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.