Method of fabricating rugged capacitor of high density DRAMs
US5923989A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1998 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | May 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
Abstract
A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers. Next, the polysilicon layer is anisotropically etched by using the rugged polysilicon layer as an etching mask to transfer rugged surface profile from the rugged polysilicon layer to the polysilicon layer. Finally, an interelectrode dielec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.