Methods to prevent divot formation in shallow trench isolation areas
US5923991A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Nov 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A number of methods to prevent divot formation, and the resulting enhanced electric field associated therewith, are disclosed. In a first embodiment of the present invention, spacers having a low etch rate in hydrofluoric acid solution, and that can be etched selectively to silicon dioxide are used to protect the silicon nitride liner from forming the divot. In a second embodiment of the present invention, a silicon dioxide spacer is used prior to the etching of the trenches, to allow the formation of the divots above the level of the silicon wafer, where they are not problematic. In a third embodiment of the present invention, a multi layer polish stop is used to prevent the formation of the divot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.