Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance

US5925914A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Chun Jiang · San Jose, US
• David Wu · San Jose, US

Key dates

• Filing date: Oct 6, 1997
• Grant date: Jul 20, 1999
• Expiry date: Oct 6, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A method of making a transistor is also disclosed, including the steps of forming a gate oxide layer (106) over a semiconductor substrate (100) and forming a gate structure (108) over a portion of the gate oxide layer (106), thereby separating the transistor into a first region (114) and a second region (112) with a channel region therebetween. The method also includes forming a source region (114) having a source LDD portion (116) and forming a drain region (112) having a drain LDD portion (124) in the second region (112), wherein the drain LDD portion (124) is more shallow than the source LDD portion (1 16). An asymmetric source/drain LDD transistor structure includes a semiconductor substrate (100), a gate oxide layer (106) overlying the substrate (100) and a gate structure (108) overlying the gate oxide layer (106). The transistor structure further includes a source region (129) and a drain region (128) formed in the semiconductor substrate (100) on opposite sides of the gate structure (108) which forms a channel region therebetween. A drain LDD region (124) is disposed between the drain region (128) and the channel and a source LDD region (116) is disposed between the source r…