Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes
US5926723A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Mar 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31056
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by using actual mask data as a reference. The invention discloses an algorithm which measures the geometric and relative separation distances of the active areas and performs the necessary merging, deletion and differential biasing to produce the planarization mask which has relaxed geometric boundaries, thereby allowing low cost and simplified manufacturing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.