Adjustable delay circuit for setting the speed grade of a semiconductor device
US5930182A · kind A · utility
46Cited by
14References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having an adjustable delay circuit such that the timing characteristics of the integrated circuit can be adjusted. A method for adjusting the timing characteristics of the integrated circuit in order to insure that the integrated circuit meets the specifications of a lower speed grade in the event that the integrated circuit fails the specifications of a targeted speed grade.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.