Method of making double-poly MONOS flash EEPROM cell
US5930631A · kind A · utility
28Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
Abstract
The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.