RAM with synchronous write port using dynamic latches
US5933369A · kind A · utility
15Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Feb 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.