Integrated circuit having forced substrate test mode with improved substrate isolation
US5933378A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/146
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit is described which includes a test mode circuit that allows a substrate of the integrated circuit to be forced to a voltage level dictated by an external connection during a test operation, and provides an improved substrate isolation from the external connection during non-test operations. Both n-channel transistor and p-channel transistor isolation circuit embodiments are described. An integrated circuit memory device is described which incorporated the test mode and isolation circuits. The external connection can be coupled to a negative voltage during non-test operation which is more negative than a threshold voltage below a substrate voltage without inadvertently coupling the external connection and substrate together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.