Vertical transistor interconnect structure and fabrication method thereof
US5933717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Mar 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
It has been discovered that improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. Etching in the vertical dimension is precisely controlled to resolutions of about 0.1 .mu.m while advanced photolithographic techniques in a volume production environment achieve resolutions of 0.25 .mu.m. Interconnect structures for connecting to high density vertical transistors are formed by depositing metal into the trenches etched during fabrication of the vertical transistors. A method of fabricating an integrated circuit includes etching a trench with a sidewall in a substrate wafer and forming a vertical transistor on the sidewall. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The method of fabricating an integrated circuit further includes forming an interconnect in the trench coupled to the vertical trans…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.