Frederick N. Hause
110Patents
26h-index
42Co-inventors
86Inventor score
Filing activity: Aug 22, 1984 → May 1, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6111260A | Method and apparatus for in situ anneal during ion implant | Electricity | 279 | Expired |
| US6274894A | Low-bandgap source and drain formation for short-channel MOS transistors | Electricity | 114 | Expired |
| US5918129A | Method of channel doping using diffusion from implanted polysilicon | Electricity | 105 | Expired |
| US6060345A | Method of making NMOS and PMOS devices with reduced masking steps | Electricity | 104 | Expired |
| US5885877A | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric | Electricity | 69 | Expired |
| US5930642A | Transistor with buried insulative layer beneath the channel region | Electricity | 68 | Expired |
| US5899732A | Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device | Electricity | 67 | Expired |
| US5888880A | Trench transistor with localized source/drain regions implanted through selectively grown oxide layer | Electricity | 63 | Expired |
| US5710054A | Method of forming a shallow junction by diffusion from a silicon-based spacer | Electricity | 59 | Expired |
| US6225151A | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Electricity | 51 | Expired |
| US6255703A | Device with lower LDD resistance | Electricity | 47 | Expired |
| US6226781A | Modifying a design layer of an integrated circuit using overlying and underlying design layers | Electricity | 45 | Expired |
| US5933721A | Method for fabricating differential threshold voltage transistor pair | Electricity | 44 | Expired |
| US5888675A | Reticle that compensates for radiation-induced lens error in a photolithographic system | Physics | 43 | Expired |
| US6268637A | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication | Electricity | 42 | Expired |
| US6084280A | Transistor having a metal silicide self-aligned to the gate | Electricity | 42 | Expired |
| US6259142A | Multiple split gate semiconductor device and fabrication method | Electricity | 41 | Expired |
| US5840451A | Individually controllable radiation sources for providing an image pattern in a photolithographic system | Emerging Cross-Sectional Technologies | 39 | Expired |
| US6410967B1 | Transistor having enhanced metal silicide and a self-aligned gate electrode | Electricity | 39 | Expired |
| US6069398A | Thin film resistor and fabrication method thereof | Electricity | 37 | Expired |
| US6080629A | Ion implantation into a gate electrode layer using an implant profile displacement layer | Electricity | 34 | Expired |
| US5933717A | Vertical transistor interconnect structure and fabrication method thereof | Electricity | 31 | Expired |
| US5512506A | Lightly doped drain profile optimization with high energy implants | Electricity | 30 | Expired |
| US5930634A | Method of making an IGFET with a multilevel gate | Electricity | 29 | Expired |
| US5801075A | Method of forming trench transistor with metal spacers | Electricity | 29 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.