Method for fabricating differential threshold voltage transistor pair
US5933721A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Apr 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
Abstract
A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.