Self-aligned silicidation structure and method of formation thereof
US5933739A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Sep 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0137
Abstract
The invention relates to integrated circuits and to methods of forming self-aligned silicidation structures. In an exemplary embodiment, a first insulating layer is formed on the surface of a semiconductor substrate which includes an electrode. A second insulating layer is formed over the first insulating layer and a photoresist pattern is formed over a silicide exclusion area. Exposed portions of the first and second insulating layers are removed by one or more etching steps, wherein an etchant used to remove the exposed portions of the second insulating layer has a higher selectivity for the second insulating layer than for the first insulating layer. A silicide layer can then be formed over the surface of the semiconductor substrate except for silicide exclusion areas. Modification of the profiles of features underlying the first insulating layer, such as sidewall spacer and field oxides can thereby be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.