Shallow trench isolation process
US5933748A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A shallow trench isolation process provides a high quality oxide on the substrate adjacent the trench and on the upper part of the trench. This process avoids the formation of poor quality oxide on the substrate adjacent the upper edge of the trench that is believed to cause MOS transistors to exhibit the undesirable subthreshold current flow known as the "kink" effect. A pad oxide layer is grown on the surface of a silicon substrate and then a layer of silicon nitride is formed on the surface of the pad oxide. A photoresist mask is formed over the silicon nitride and the silicon nitride and pad oxide are etched, and then the substrate is etched to form a trench. The photoresist mask is removed, a layer of polysilicon is deposited over the silicon nitride layer and within the trench and the polysilicon layer is oxidized. CVD oxide is deposited to overfill the trench and then the excess CVD oxide and polysilicon oxide is removed by CMP, using the silicon nitride layer as an polish stop. The silicon nitride is stripped and the trench oxide is etched using an HF dip to provide a substantially planar surface. A layer of polysilicon is deposited on the device and doping, patterning and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.