Via structure using a composite dielectric layer
US5935876A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Jun 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.