High-capacitance dynamic random access memory cell having a storage capacitor on a continuous irregular surface

US5936273A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Anchor Chen · Pingtung City, TW

Key dates

• Filing date: Jul 24, 1997
• Grant date: Aug 10, 1999
• Expiry date: Jul 24, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/31

Abstract

A semiconductor structure for a DRAM cell having a high capacitance capacitor. The DRAM cell includes a silicon substrate on which a field oxide layer and a transistor having a gate layer and a source/drain region are formed. A contact surface is formed on a surface of the source/drain region. A silicon nitride layer is formed over the gate layer. A thick oxide layer is formed over one part of the silicon nitride layer, at a lateral side of the contact surface. Silicon nitride spacers are formed over opposite lateral sides of the gate layer, the silicon nitride layer, and the thick oxide layer. One of the silicon nitride spacers located adjacent to the contact surface, is shaped in the form of a pointed protrusion. A self-aligned contact insulating layer covers the thick oxide layer and the other silicon nitride spacer, that is located away from the contact surface. This structure defines a jagged surface over at least the contact surface, the pointed protrusion and the silicon nitride layer. A high surface area capacitor structure, including a first conductive layer, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer, is the…