Method for reducing stress in the metallization of an integrated circuit

US5939335A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kenneth C. Arndt · Fishkill, US
• Richard A. Conti · Altamont, US
• David M. Dobuzinsky · New Windsor, US
• Laertis Economikos · Hopewell Junction, US
• Jeffrey P. Gambino · Gresham, US
• Peter D. Hoh · Hopewell Junction, US
• Chandrasekhar Narayan · Hopewell Junction, US

Key dates

• Filing date: Jan 6, 1998
• Grant date: Aug 17, 1999
• Expiry date: Jan 6, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76885
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.