Ultrathin oxynitride structure and process for VLSI applications
US5939763A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1996 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Sep 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.