Input buffer
US5939900A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer which is coupled to a direct voltage source and ground, includes at least one CMOS device and an enhancement mode NMOS transistor, receives at least one input signal and provides one output signal. The input buffer makes use of the enhancement mode NMOS transistor to lower the potential difference between the gate terminal and the source terminal of the PMOS transistor of the CMOS device. Thus, the input buffer can lower the turning on degree of the PMOS transistor effectively. Then the PMOS transistor which is considered as a pull-up transistor can lower the degree to which the input buffer is turned on, and maintain the characteristics and functionality of the input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.