Memory interface circuit including bypass data forwarding with essentially no delay
US5940334A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and operating technique acquires input write data available at the beginning of the first half cycle and passes the write data to read terminals, bypassing read data from a memory cell that is read during the first half cycle, while incurring no read access penalty. The circuit and operating technique bypass the input write data to the read terminal in place of data transferred from the memory cells. The data is forwarded to an node having a relatively large capacitance by connecting to the node very small devices with a small capacitance and with the small devices operating in saturation. The relatively large capacitance of the node is exploited to achieve a multiplexing functionality with effectively no delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.