Small gate electrode MOSFET
US5942787A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1996 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Nov 18, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material. Sidewall spacers are formed in the conformal layer proximate side edges of the patterned layer, the sidewall spacers having a desired line width dimension of the small features to be fabricated. The patterned layer is thereafter selectively removed. The first layer is then directionally etched with a selective etch, using the sidewall spacers to prevent the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.