FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines
US5942913A · kind A · utility
71Cited by
58References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Mar 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some buffered interconnect lines are bidirectional, and others are unidirectional. A carefully selected mixture of unidirectional and bidirectional lines provides a balance of flexibility, silicon area, and performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.