Method for fabrication of shallow isolation trenches with sloped wall profiles
US5945352A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.