Method of forming a capacitor

US5946571A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chen-Chiu Hsue · Baoshan, TW
• Sun-Chieh Chien · Hsinchu, TW

Key dates

• Filing date: Nov 21, 1997
• Grant date: Aug 31, 1999
• Expiry date: Nov 21, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A DRAM capacitor is formed having a crown structure with a reduced number of processing steps. A planarized insulating layer is provided over the DRAM cell's transfer FET and a contact via is opened to one of the source/drain regions of the transfer FET. A layer of polysilicon is deposited to fill the contact via and to extend over the surface of the insulating layer, providing a thick polysilicon layer on the insulating layer. Conventional photolithography is used to define a first etching mask with an element on the thick polysilicon aligned over the contact via. The polysilicon layer is etched partially through using the first etching mask and the photoresist mask is removed. A layer of oxide is deposited over the elevated and recessed surfaces of the polysilicon layer and an etch back process is performed to form a second etching mask consisting of oxide spacer structures along the edges of the elevated portion of the polysilicon layer. Etching of the polysilicon layer is performed using the second etching mask, with the etch step proceeding completely through the recessed portions of the polysilicon layer and partially through the elevated portion of the polysilicon layer. The…