Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process
US5949143A · kind A · utility
68Cited by
5References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 22, 1998 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jan 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure capable of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The structure comprises at least first and second metal regions separated by a dielectric region, an air gap formed at least partially within the dielectric region, a diffusion barrier positioned over the two metal regions covering a portion of the upper surface of the air gap, and an insulating layer positioned over the diffusion barrier sealing the upper surface of the air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.