Test head for applying signals in a burn-in test of an integrated circuit
US5949246A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jan 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.