Adjustable output driver circuit
US5949254A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 26, 1996 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Nov 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output driver circuit offers wave-shaping and logic level adjustment for high speed data communications in a synchronous memory such as a dynamic random access memory (DRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Wave-shaping functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different wave-shaping characteristics of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.