Method for fabricating a metal-oxide semiconductor transistor
US5950090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1998 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Nov 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining porti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.