Integrated circuit tester having pattern generator controlled data bus
US5951705A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits. The tester circuits perform test activities on an integrated circuit in response to sequences of test control data arriving via a set of data lines. The host computer may write parameter control data into the tester circuits via a bus telling the tester circuits how to adjust various parameters of test activities to be performed in response to a next arriving sequence of test control data. The host computer is also linked to the pattern generator via that same bus and writes pattern control data into the pattern generator via the bus. The pattern control data tells the pattern generator to generate alternating sequences of test control data and pattern control data. As it is generated, each test control data sequence is delivered to the tester circuits via the data lines to tell the tester circuits how to carry out a sequence of test activities. As each parameter control data sequence is generated, the parameter control data is written into the tester circuits via the bus to set the test parameters for a next sequence of test activities to be performed. Thus once programmed with…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.