Method and apparatus for implementing engineering change orders in integrated circuit designs
US5953236A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1995 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (a) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (b) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (c) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (i) modifying the netlist pursuant to an engineering change order (ECO); and (ii) making an ECO placement of at least one cell into the layout area based upon the timing constraints while adjusting any affected nets as specified by the netlist. A layout tool implements the method on a computer system to form a portion of and integrated circuit fabrication system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.