Air voids underneath metal lines to reduce parasitic capacitance
US5953625A · kind A · utility
20Cited by
5References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Dec 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.