Method of fabricating vertical FET with Schottky diode
US5956578A · kind A · utility
64Cited by
1References
16Claims
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Assignee
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Key dates
| Filing date | Apr 23, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Apr 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/01
Abstract
A method of fabricating an integrated VFET and Schottky diode including forming a source region on the upper surface of a substrate so as to define a channel. First and second spaced apart gates are formed on opposing sides of the source region so as to abut the channel, thereby forming a channel structure. Schottky metal is positioned on the upper surface of the substrate proximate the channel structure to define a Schottky diode region and form a Schottky diode. A source contact is formed in communication with the source region and the Schottky metal, and a drain contact is formed on the lower surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.