Process of forming a field effect transistor without spacer mask edge defects
US5956590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Aug 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor which is not susceptible to mask edge detects at its gate spacer oxides. The transistor is formed upon a semiconductor substrate through successive layering of a gate oxide, a gate electrode and a gate cap oxide. A pair of curved gate spacer oxides are then formed covering opposite edges of the stack of the gate oxide, the gate electrode and the gate cap oxide. The semiconductor substrate is then etched to provide a smooth topographic transition from the gate spacer oxides to the etched semiconductor surface. Source/drain electrodes are then implanted into the etched semiconductor substrate and annealed to yield the finished transistor. A second embodiment of the field effect transistor possesses a polysilicon gate. Alter removal of the gate cap oxide, a metal layer may be deposited and sintered upon the polysilicon gate and the source/drain electrodes. The metal salicide layers formed upon the electrodes of the transistor have limited susceptibility to parasitic current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.