Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
US5956603A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1998 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Aug 27, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a plurality of shallow-junction metal oxide semiconductor field-effect transistors (MOSFETs) on a selected area of a silicon wafer, in the case in which the MOSFETs are spaced from one another by substantially transparent isolation elements. The method includes the step of flooding the entire selected area with laser radiation that is intended to effect the heating to a desired threshold temperature of only the selected depth of a surface layer of silicon that has been previously amorphized to this selected depth and then doped. This threshold temperature is sufficient to melt amorphized silicon but is insufficient to melt crystalline silicon. However, should the laser radiation be directly incident on both the substantially transparent isolation elements and the silicon surface, a variable portion of the energy of the incident radiation traveling through the substantially transparent isolation elements would be transferred to the silicon surfaces in contact with the isolation elements depending on the depth of the isolation elements thereby causing unpredictable additional heating of the silicon which would result in an unwanted shift in the fluence requir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.