Modulating surface morphology of barrier layers
US5956608A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Jun 20, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/906
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating electronic devices which includes the steps of providing a structure that includes a substrate with an overlying dielectric layer having one or more contact holes and/or vias formed therein; depositing a barrier layer over the structure so that the barrier layer penetrates into the contact holes and/or vias; plasma etching the deposited barrier layer so as to modify its surface morphology; and after modifying the surface morphology of the deposited barrier layer, depositing a metalization layer over the barrier layer. A two-step preclean to facet upper corners of the holes and/or vias and to clean bottoms of the holes and/or vias is performed prior to the deposition of the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.