Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US5956609A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Aug 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is described for improving the step coverage of tungsten interconnects and plugs when deposited at low temperatures into contact/via openings having high aspect ratios. The depositions are made at pressures between 4.5 and 100 Torr in a CVD tool. The method includes a first nucleation step, and a second step for filling the contact/via openings wherein deposition conditions favor good step coverage. For forming an interconnect and a third deposition step, providing moderate step coverage and low stress, is used to build up the interconnect. The high pressures permit deposition at practical rates at low temperatures. In addition the high pressures also permit application of backside gas pressure to the wafer during deposition, thereby improving the thermal contact between the wafer and the heated substrate holder. This contributes significantly to stress reduction and improved step coverage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.