Decoder circuit with short channel depletion transistors
US5959336A · kind A · utility
42Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1996 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Aug 26, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/907
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.