Checkpoint table for selective instruction flushing in a speculative execution unit
US5961636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Sep 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.