System for distributing clocks using a delay lock loop in a programmable logic circuit
US5963069A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Nov 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.