Programmable delay circuit having calibratable delays
US5963074A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements connected in series for successively delaying the INPUT signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage. The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.