Microelectronic packaging using arched solder columns
US5963793A · kind A · utility
72Cited by
42References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/306
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Microelectronic packages are formed wherein solder bumps on one or more substrates are expanded, to thereby extend and contact the second substrate and form a solder connection. The solder bumps are preferably expanded by reflowing additional solder into the plurality of solder bumps. The additional solder may be reflowed from an elongated, narrow solder-containing region adjacent the solder bump, into the solder bump. After reflow, the solder bump which extends across a pair of adjacent substrates forms an arched solder column or partial ring of solder between the two substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.