Combined trench isolation and inlaid process for integrated circuit formation
US5963818A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Sep 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an integrated circuit involves forming trench isolation regions (208a) and a damascene gate electrode region (214) simultaneous with one another via overlapping process steps. By performing this simultaneous formation of a trench region (208a) and a damascene gate electrode (214) using a common dielectric layer (208), MOS integrated circuits can be formed with reduced processing steps while simultaneously avoiding adverse polysilicon stringers which are present in prior art damacene-formed gate electrode. A single dielectric layer (208) is deposited in order to provide trench fill material for a trench region (208a) while simultaneously providing the material needed for form an opening (210) which is used to define the dimensions and material content of a gate electrode (214).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.