Apparatus and method for programming PMOS memory cells
US5966329A · kind A · utility
36Cited by
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17Claims
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Key dates
| Filing date | Oct 9, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Oct 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program voltage of a first level is applied to the control gate of a PMOS floating gate memory cell to realize an injection of hot electrons induced by band-to-band tunneling (BTBT) into the floating gate of the cell. As the threshold voltage of the cell increases due to the accumulation of charge on the floating gate, the injection of BTBT induced hot electrons subsides. The program voltage is reduced to a second level which induces the injection of channel hot electrons (CHE) into the floating gate, thereby boosting the rate of charge accumulation on the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.